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High-k and Low-k Gate Dielectric Stacking for Low Voltage Organic Thin Film Transistors

Shagun Pal, Brijesh Kumar

Abstract


Electrical performance parameters of Organic thin film transistor (OTFT) are closely related to the interface characteristics of gate dielectric and organic semiconductor film. Henceforth, it becomes important to study the effect of gate dielectric stacking on device performance of OTFTs. In this paper, we demonstrate the stacking of high-k and low-k gate dielectric based Single and Dual gate OTFTs. The structural effect of Organic thin film transistors is methodically explored by varying the electrical properties as well as by varying thickness of each dielectric layer. The two dimensional (2D) numerical device simulator is used to investigate the behavioral changes of these devices and it has found that leakage current decreases drastically by the stacking engineering. Subsequently, this reduction in leakage current improves the threshold voltage VTH from 0.81 V to 0.50 V which is the important factor for the switching application in organic digital applications. This systematic approach consequently will be helpful in recognizing the device in practical applications.

Keywords


High-k, Low-k, Leakage current, Dielectric, OTFTs.

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References


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