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Magnetic Priority Encoder Based on Spin Devices

Yogendra Kumar Upadhyaya, Austosh Tripathi, Arun Kishor Johar

Abstract


Energy dissipation has already become an important consideration in the design of digital integrated circuits. Because current-induced domain-wall (DW) motion is a common switching mechanism, high-density, low-power, and high-speed circuits are possible. Because spin computing is one of the most common sources of energy dissipation, employing spin logic to design digital circuits is an effective way to reduce the circuit's energy dissipation. As a result, a new spin-based priority encoder design is proposed. Domain wall motion-based magnetic strips are being used to address the requirement for ultra-low power, area-efficient, and high-speed priority encoders in order to improve speed and power efficiency. Designers can employ analytical expression to get a sense of the primary contributors of priority encoders (PEs) and thoroughly investigate the trade-offs (PEs).


Keywords


PCSA; PE; MTJ; Spin devices; Spin logic

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References


S. S. P. Parkin, M. Hayashi, and L. Thomas, “Magnetic domain-wall racetrack memory,” Science, vol. 320, pp. 190–194, Apr. 2008.

E. Atoofian, “Reducing shift penalty in domain wall memory through register locality,” in Proc. Int. Conf. Compil., Archit. Synth. Embedded Syst. (CASES), Piscataway, NJ, USA, 2015, pp. 177–186.

S. Ikeda et al., “A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction,” Nat. Mater., vol. 9, no. 9, pp. 721–724, Sep. 2010.

Y. Zhang, W.S. Zhao, “Perpendicular-Magnetic-anisotropy CoFeB racetrack memory” Journal of applied physics111,15 May 2012.

Yogendra Kumar Upadhyaya, Mohit Kumar Gupta, Mohd. Hasan, Sudhanshu Maheshwari “High-Density Magnetic Flash ADC using Domain Wall Motion and Pre-Charge Sense Amplifiers” IEEE Transaction on Magnetics Volume: 52, Issue: 6, Year: 2016,

B. Razavi, and B.A. Woody, “Design techniques for high-speed, high-resolution comparators”, IEEE Journal of Solid-State Circuits, Volume 27, Issue 12, pp.1916–1926, Dec. 1992

Mohit Kumar Gupta, Mohd. Hasan, “Robust High-Speed Ternary Magnetic Content Addressable Memory,” IEEE Transaction on Electron Devices, Vol. 62, Issue 4, pp. 1163-1169, April, 2015.

Mohit Kumar Gupta, Mohd. Hasan, “Design of high-speed energy efficient masking error immune PentaMTJ based TCAM” IEEE Transaction on Magnetics, Vol. 51, No. 2, 3400209, Feb., 2015.

Mrigank Sharad and Kaushik Roy “Spintronic Switches for Ultralow Energy On-Chip and Interchip Current-Mode interconnects”, IEEE Electron Device Letters, vol. 34, No. 8, August 2013.

S. Parkin et al, “Memory on the racetrack” Nature Nano., vol. 10, March, 2015.

J.-S. Wang and C.-H. Huang, “High-speed and low-power CMOS priority encoders,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp.1511– 1514, Oct. 2000.

Kun, S. Quan, and A. Mason, “A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead,” in Proc. 2004 IEEE Int. Symp. Circuits Syst. (ISCAS’04), May 23–26, 2004, vol. 2, pp. II-753–6..

D. H. Summerville, J. G. Delgado-Frias, and S. Vassiliadis, “A flexible bit-pattern associative router for interconnection networks,” IEEE Trans. Parallel Distrib. Syst., vol. 7, pp. 447–485, May 1996.

Yue Zhang, Weisheng Zhao, Yahya Lakys, Jacques-Olivier Klein, Joo- Von Kim, Dafiné Ravelosona, and Claude Chabert, “Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions” IEEE Transaction on Electron Devices, Vol. 59, Issue 3, pp. 169-177, March 2012.

C.-H. Huang, J.-S. Wang, and Y.-C. Huang, “Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques,” IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 63–76, Jan. 2002.

Xiaoyu Wang, Yukang Feng, " C.-H. Huang, J.-S. Wang, and Y.-C. Huang, “Analysis and Design of 8-Bit CMOS Priority Encoder,” https://doi.org/10.48550/arXiv.1806.01443, Jan. 2018.

J. G. Delgado-Frias and J. Nyathi, “A VLSI high-performance encoder with priority lookahead,” in Proce. 8th Great Lakes Symp. VLSI, Feb. 19–21, 1998, pp. 59–64.

R. Hashemian, “A high-speed compact priority encoder,” in Proc. 32nd Midw. Symp. Circuits Syst., Aug. 14–16, 1989, vol. 1, pp. 197–200.

J. G. Dekgado-Frias and J. Nyathe, “A high-performance encoder with priority lookahead,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 9, pp. 1390–1393, Sep. 2000.

Y. Zhang, W.S. Zhao, “Perpendicular-Magnetic-anisotropy CoFeB racetrack memory” Journal of applied physics111, 15 May 2012.

Yue Zhang, Weisheng Zhao, YahyaLakys, Jacques-Olivier Klein, Joo-Von Kim, DafinéRavelosona, and Claude Chappert, “Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions”, IEEE Transaction on Electron Devices, Vol. 59, Issue 3, pp. 169-177, March 2012.

J.-S. Wang and C.-S. Huang, “A high-speed single-phase-clocked CMOS priority encoder,” in Proc. 2000 IEEE Int. Symp. Circuits Syst. (ISCAS’00), May 28–31, 2000, vol. 5, pp. 537–540.


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